This invention relates to a clock control technique for a semiconductor integrated circuit and, more particularly, to a synchronous delay circuit for controlling clock signals and to a semiconductor integrated circuit apparatus having such synchronous delay circuit.
A synchronous delay circuit for eliminating clock skew within a short synchronous time period has come to be used in the high-speed clock synchronization circuit because of its simplified circuit structure and only low power consumption. For this sort of the synchronous delay circuit, reference may be had e.g., to the following publications:
[1] JP Patent Kokai JP-A-8-237091;
[2] JP Patent Kokai JP-A-11-73238 (U.S. Pat. No. 6,075,395);
[3] Jin-Man Han et al., Skew Minimization Technique for 256M-bit Synchronous DRAM and Beyond, 1996 Symp. on VLSI Circ. pp. 192-193;
[4] Richard B. Watson et al., Clock Buffer Chip with Absolute Delay Regulation Over Pricrss and Environment Variations, Proc. of IEEE 1992 CICC (Custom Integrated Circuits Conference), 25.2;
[5] Yoshihiro OKAJIMA et al., Digital Delay locked Loop and Design Technique for High-Speed Synchronous Interface, IEICE TRANS. ELECTRON., Vol. E79-C, No. 6, June 1996, pp. 798-807.
FIG. 5 shows an illustrative structure of a semiconductor integrated circuit having a conventional synchronous delay circuit. Meanwhile, the structure shown in FIG. 5 is based on the structure of the synchronous delay circuit described in the publication [2] (JP-A-11-73238) filed by the same applicant.
A synchronous delay circuit 100 includes, as its basic structure, a first delay circuit delay circuit chain 11 for period (delay) measurement, adapted for Propagation of clock Pulses or clock Pulse edges therein, and a second delay circuit chain 12 for delay reproduction, capable of propagation of pulses or pulse edges by a length corresponding to a length of the propagation of the pulse or pulse edges through the first delay circuit chain 11.
The configuration shown in FIG. 5 is designed so that the clock period tCK of the input clocks 3 less the delay tCTS of a clock tree 4, as detected by a delay detection circuit 5 as later explained, or tCKxe2x88x92tCTS, is measured by the synchronous delay circuit 100, in consideration of fluctuations in the propagation delay time of the clock tree 4, to realize clocks substantially free of skew with respect to input clocks 4 even if the propagation delay time tCTS of the clock tree 4 is changed.
In designing a semiconductor integrated circuit, there is used e.g., the designing by the clock tree synthesis (CTS) method of optimally introducing a buffer for equalizing the delay in the clock signal wiring network to provide a tree-like layout, in order to minimize the difference in clock signal delay time, in such a manner as to distribute clock signals in respective clock using circuits, such as flipflops. The clock tree 4 is made up of clock wiring routes laid out in a tree fashion. In FIG. 5, a triangular symbol of the clock tree 4 schematically denotes a buffer inserted in the clock tree for equalizing the delay in driving the load. It should be noted that the clock tree 4 is shown only schematically such that the number of stages of the buffer circuits comprehended in the clock tree 4 is not necessarily limited to four. In FIG. 5, A denotes an input node of the clock tree 4 and B a preset output node, such as a maximum delay node, as selected as a control object in the clock tree 4. Meanwhile, the clock propagation Path arranged in the clock tree 4 might be any suitable clock signal-wiring route in a semiconductor integrated circuit, without being limited to the signal-wiring path for clock propagation by e.g., the CTS wiring method.
Referring to FIG. 5, showing a semiconductor integrated circuit apparatus, when an input clock 3 (IN), fed from e.g., a clock driver, not shown, is fed through a changeover unit 10 to an input node A of a clock tree 4, a delay detection circuit for inputting the clock signal to its first input terminal resets or inactivates its output D (also termed a monitoring signal), with the delay circuit chain 11 then halting the propagation of the clock signals.
When the clocks fed to a node A of the clock tree 4 reaches the node B after the propagation delay time tCTS, the delay detection circuit 5. fed with the clock signals in its second input terminal, sets (activates) its output D and, responsive to this output D, the delay circuit chain 11 permits the clock propagation.
FIG. 6 shows an illustrative structure of a synchronous delay circuit 100 and the delay detection circuit 5 shown in FIG. 5. Referring to FIG. 6, the synchronous delay circuit 100 includes a first delay circuit chain 11 made up of plural unit delay elements, for transmitting pulses or pulse edges of input clocks (IN) and for issuing an output at an arbitrary position of the transmission path, a second delay circuit chain 12, similarly made up of plural unit delay devices, for being fed at an arbitrary position of the transmission path with clock Pulses and pulse edges for transmission, and a control circuit array 18, made up of plural control circuits, each having a signal input terminal, a signal output terminal and an input/output control terminal. The first and second delay circuit chains 11, 12 are designed so that the respective signal transmission paths are reversed in the signal propagation direction to each other. Moreover, the first delay circuit chain 11 and the second delay circuit chain 12 are interconnected through the control circuit array 18 so that the sides of the first delay circuit chain 11 closer to an input end of clocks IN are connected to the sides of the second delay circuit chain 12 closer to an output end of the clocks, and so that, at a time point when the clock signal input to the first delay circuit chain 11 has propagated a preset time as from the time point of inputting of the signal to the first delay circuit chain 11 that is at a time point when the next clock signal is input, a signal is input to the input/output control terminal of the control circuit array 18 at a position to which the clock signal has propagated so that the clock signal propagating through the first delay circuit chain 11 is input and transferred into the second delay circuit chain 12 from the Position corresponding to the propagated (traversed) position.
In the embodiment shown in FIG. 6, the delay circuit chain 11 for delay measurement and the delay circuit chain 12 for delay reproduction (reconstruction) are arranged in reverse directions to each other. Of course, the present invention is not limited to this configuration. A pair of delay circuit chains through which signal propagation occurs in the same direction may also form the synchronous delay circuit in the known manner. Reference may be had to the above-mentioned publications for alternative construct ions of the synchronous delay circuit, the entire disclosures thereof being incorporated in the present invention by reference thereto.
In the first delay circuit chain 11, in which a clock pulse has been input from the input end C, the clock pulse progresses through the inside of the first delay circuit chain 11 and, when a clock pulse next following the propagating clock pulse is input, the control circuit array 18 is activated responsive to this next clock pulse to transfer the clock pulse from the position in the first delay circuit chain 11 through which it is propagating through the control circuit array 18 registering with this position to the second delay circuit chain 12. The clock Pulse transferred to the second delay circuit chain 12 progresses through the second delay circuit chain 12 in a reverse direction to the propagating direction of the clock pulse through the first delay circuit chain 11 and is issued as output. In the embodiment shown in FIG. 6, a clock pulse progresses through the inside of the delay circuit chain 11 for delay measurement a number of delay circuits, shown by hatching, herein three delay circuits, in a given direction, herein in a direction of an arrow xe2x86x92 and, responsive to the next clock input (IN), the clock pulse is transferred to the delay circuit chain 12 for delay reproduction (reconstruction), so as to propagate through three delay circuits of the delay circuit chain 12, shown by hatching, in the opposite direction indicated by an arrow ←. before it is issued as output.
The delay detection circuit 5 is formed as a set-reset (SR) flipflop or latch circuit having its reset (R) terminal and set (S) terminal connected to an input node A and to an output node B of the clock tree 4, respectively. When a clock pulse reaches the input node A of the clock tree 4, the delay detection circuit 5 is reset so that the control signal (monitor signal) goes Low. Similarly, when the clock pulse reaches the node B of the clock tree 4, the delay detection circuit 5 is set so that the control signal D goes High.
The operation of the conventional synchronous delay circuit, explained in connection with FIGS. 5 and 6, is now explained with reference to the timing diagram of FIGS. 7 and 8.
If the propagation delay time tCTS of the clock tree 4 is smaller than the clock period tCK (tCTS less than tCK), a timing waveform as shown in FIG. 7 is obtained. In FIG. 7, IN, A and B denote an input clock 3, an input node A of the clock tree 4 and a clock signal waveform of the output node B, respectively.
First, the switching over unit 10 selects the clock 3 (IN) and, as from the time point the clock signal is input to the node A of the clock tree 4, the output of the delay detection circuit 5 is reset for a delay time tCTS of the clock tree 4, with the unit delay element (clocked inverter) in the first delay circuit chain 11 being turned off. At a time point after lapse of tCTS, when the clock signal reaches the node B of the clock tree 4, the output of the delay detection circuit 5 is set, with the clocked inverter forming the unit delay element in the first delay circuit chain 11 being turned on.
Referring to FIG. 7, the first clock of the input clocks IN progresses through the first delay circuit chain 11 for a time interval tCKxe2x88x92tCTS and, responsive to the second clock of the input clocks IN, the first clock is transferred through the control circuit 18 to the second delay circuit chain 12 as from a position (time point) corresponding to (tCKxe2x88x92tCTS). The first clock then progresses through the second delay circuit chain 12 for a reproduction time period of (tCKxe2x88x92tCTS) before it is issued as output. The output first clock is fed through the switching over unit 10 to the node A of the clock tree 4.
The rising edge of the clock input to the node A of the clock tree 4 is delayed from the input clock IN by the reproduction time (tCKxe2x88x92tCTS).
FIG. 8 illustrates the operation when the propagation delay time tCTS of the clock tree 4 is longer than the clock period tCK.
In this case, a clock reaches the node B after lapsing of the propagation delay time tCTS of the clock tree 4 as from the clock inputting time point to the node A of the clock tree 4. That is, until a time equal to one clock cycle tCK and further encroaching a time tCTSxe2x88x92tCK into the next clock cycle, the first delay circuit chain 11 is responsive to the output of the delay detection circuit 5 to stop (cease) the clock propagation. As from the time point of tCTSxe2x88x92tCK within the next clock cycle, the first delay circuit chain 11 begins propagating an input clock, specifically a second clock pulse of the input clock IN of FIG. 8. This second clock pulse progresses through the first delay circuit chain 11 of the synchronous delay circuit 100 until the next clock pulse, specifically a third clock pulse of the input clocks IN of FIG. 8, is input to the synchronous delay circuit 100.
That is, at a time Point when the clock (second clock pulse of the input clocks IN of FIG. 8) has Propagated through the first delay circuit chain 11 for a time interval of tCKxe2x88x92(tCTSxe2x88x92tCK)=2tCKxe2x88x92tCTS, the second pulse is transferred, from a position corresponding to the measured time 2tCKxe2x88x92tCTS in the first delay circuit chain 11, into the second delay circuit chain 12 for reproduction, responsive to the next clock pulse (third clock pulse of the input clocks IN of FIG. 8). The second clock pulse is transferred through the second delay circuit chain 12 for a reproduction time duration of 2tCKxe2x88x92tCTS so as to be output from the second delay circuit chain 12 and so as to be input to the node A of the clock tree 4 through the switching over unit 10 (second clock pulse shown at A in FIG. 8). Meanwhile, a third clock pulse at the node A in FIG. 8 is a clock signal corresponding to a second clock pulse of the input clocks IN of FIG. 8, that is, input to the first delay circuit chain 11, turned back at the measurement time, propagated for the reproduction time and output from the second delay circuit chain 12 to reach the node A of the clock tree 4.
After synchronization, clock signals are fed to the node A of the clock tree 4 at a timing (phase) which leads the rising edge of the input clock IN by a time interval of tCKxe2x88x92(2tCKxe2x88x92tCTS)=tCTSxe2x88x92tCK.
The synchronous delay circuit is basically made up of a circuit set comprised of a pair of delay circuit chains (or queues), as described above.
There is also known a configuration comprised of two sets of the synchronous delay circuits. In these two sets of the synchronous delay circuits, equal delay quantities are used as detected period quantities. As a structure comprised of two sets of the synchronous delay circuits, such a structure as disclosed e.g., in JP Patent Kokai JP-A-11-73238, and as shown herein for example in FIG. 10, is known. The circuit shown in FIG. 10 measures the clock periods using clock pulse edges. Specifically, the circuit shown in FIG. 10 includes two sets of delay circuit chains and frequency divides the clocks by a frequency divider 24 to run the delay circuit chains alternately, chain by chain, at an interval of one period.
In the course of further researches toward the present invention, certain problems have been encountered.
Namely, the above-described conventional synchronous delay circuit has a drawback that the delay time tCTS of the clock tree 4 is set so as to be approximately equal to the clock period tCK, such that, if the clock period becomes longer or shorter than the delay of the clock tree due to, for example, jitter, the clocks are subjected to discontinuities in propagation.
The clock period tCK becomes shorter with an increasing operating frequency of a semiconductor integrated circuit, whilst the delay time tCTS of the clock tree 4 increases with increasing popularity of the clock using circuit, such that there will be an increasing number of occasions in future wherein the delay time tCTS of the clock tree 4 is approximately equal to the clock period tCK. It is therefore required to prevent erroneous circuit operation due to clock supply interrupt ions caused when the clock period fluctuates, i.e., becomes longer or shorter than the delay quantity of the clock tree. This will be elucidated in the following.
FIG. 9 illustrates the timing operation in a conventional synchronous delay circuit, explained e.g., with reference to FIG. 5, wherein the propagation delay time tCTS of the clock propagation path 4 is approximately equal to the clock period tCK of the input clock 3 (IN) and wherein such fluctuations as tCTS greater than tCK or tCTSxe2x89xa6tCK occur, e.g., following a synchronization.
If tCTS less than tCK, as shown in FIG. 9, the node A of the clock propagation path 4 is fed with a clock rising with a delay equal to the reproducing time tCKxe2x88x92tCTS as from the rising edge of the clock input IN. If tCTS greater than tCK due, e.g., to jitter, the measuring time of the first delay circuit chain 11 (see FIG. 5) is 2tCKxe2x88x92tCTS, as stated previously. Thus, responsive to the clock signal fed to the first delay circuit chain 11, the clock is transferred from this position in the first delay circuit chain 11 to the second delay circuit chain 12 for reproduction, such that, after the reproducing (reconstructing) time of 2tCKxe2x88x92tCTS, the clock is issued as output from the second delay circuit chain 12 so as to be fed via switching over unit 10 to the node A of the clock propagation path 4.
In this case, clock supply interruptions (clock discontinuities) are produced at the input node A of the clock propagation path 4 fed with clocks from an output terminal of the synchronous delay circuit 100.
Should the clock supply interruptions (clock discontinuities) be produced in this manner, circuit malfunctions are produced in the synchronization circuit.
It is therefore a principal object of the present invent ion to provide a synchronous delay circuit in which, even if the clock period is approximately equal to the delay time of the clock propagation path, and if the clock tree delay time becomes longer or shorter than the clock period, due to, e.g., jitter or skew variations, it is reliably possible to prevent the clock discontinuities. Other aspects, objects, advantages and features of the present invention will be apparent from the following description of the present invention and the claims.
According to an aspect of the present invention, there is provided a synchronous delay circuit apparatus including a plurality of sets of synchronous delay circuits, each set including a first delay circuit chain for delay measurement, along which input clock signals propagate, and a second delay circuit chain, using the first delay circuit chain the difference being measured between the delay time of a preset circuit or path for propagating and outputting clocks and the period of input clocks, the second delay circuit chain reproducing and outputting the measured time difference. At least one of the sets of the synchronous delay circuits, being added with delay, has a measured delay quantity different from that of the other or others of the synchronous delay circuits, so that, even when the relative relation in the magnitudes between the delay time of the preset circuit or path and the Period of the input clock is changed, there is no discontinuity in clocks output from the synchronous delay circuits to the preset circuit or path.
According to a second aspect of the present invention, there is provided a synchronous delay circuit apparatus including a plurality of sets of synchronous delay circuits, each set including a first delay circuit chain for delay measurement, along which input clock signals propagate, and a second delay circuit chain for period reproduction for allowing the clock signals to pass therethrough a length corresponding to the length of propagation of the clock signals through the first delay circuit chain, and
delay detection circuits each associated with each of the synchronous delay circuits. The delay detection circuit detects the propagation delay time required for propagating clocks from an input node to a preset output node of a preset clock propagation path, the delay detection circuit outputting a control signal for controlling the synchronous delay circuit to halt the propagation of clock signals in association with the propagation delay time.
There is introduced delay to an input of at least one of the Plural delay detection circuits to differentiate the delay time as detected in the one delay detection circuit from the delay time detected by the other delay detection circuits to differentiate the detected period quantity in the synchronous delay circuit associated with the one delay detection circuit from the detected period quantity detected in the synchronous delay circuit associated with each of the other delay detection circuits, so that, even if the propagation delay time in the clock propagation path becomes longer or shorter than the clock period, no discontinuity is produced in the clocks supplied from the synchronous delay circuit to the clock propagation Path.
According to a third aspect, there is provided a synchronous delay circuit apparatus comprising:
(a) two sets of synchronous delay circuits, each set including a first delay circuit chain for period measurement for propagation of pulses or pulse edges of input clock signals and a second delay circuit chain for period reproduction, the second delay circuit chain allowing pulses or pulse edges of clock signals to propagate therethrough by a length corresponding to the length traversed by the pulses or pulse edges of the clock signals through the first delay circuit chain; and
(b) two delay detection circuits provided in association with the synchronous delay circuits, respectively, each delay detection circuit detecting the propagation delay time in propagating the clocks from the input node to a preset output node of a clock propagation path and outputting a control signal for controlling the synchronous delay circuit to cease the propagation of the pulses or pulse edges of input clock signals in association with the propagation delay time;
(c) wherein delay is introduced to an input of at least one of the plural delay detection circuits to differentiate the delay time as detected in the one delay detection circuit from the delay time detected by the other of the delay detection circuits to differentiate the period in the synchronous delay circuit associated with the one delay detection circuit from the detected period quantity detected in the synchronous delay circuit associated with each of the the other of the delay detection circuits, so that, even when the propagation delay time in the clock propagation path becomes longer or shorter than the clock period, no discontinuity is produced in the clocks supplied from the synchronous delay circuit to the clock propagation path.
There is provided a switching over unit for switching over between an output of each second delay circuit chain of each synchronous delay circuit, and an output of the switching over unit is connected to an input node of the clock propagation path.
The delay detection circuit comprises a flipflop that is reset responsive to clock inputting to an input node of the clock propagation path and set responsive to an output of the clock from an output node of the clock propagation path.
According to a fourth aspect, there is provided a semiconductor integrated circuit apparatus in which a clock signal supplied to a clock propagation path is control led using a synchronous delay circuit, the semiconductor integrated circuit comprising:
(a) a plurality of sets of synchronous delay circuits, each set including a first delay circuit chain for period measurement, along which input clock signals propagate, and a second delay circuit chain, for period reproduction, allowing the clock signals to pass therethrough a length corresponding to the length of propagation of the clock signals through the first delay circuit chain; and
(b) delay detection circuits each associated with each of the synchronous delay circuit, the delay detection circuits each detecting the propagation delay time required for propagating clocks from an input node to a preset output node of a preset clock propagation path, the delay detection circuits each outputting a control signal for controlling the synchronous delay circuit to cease the propagation of clock signals in association with the propagation delay time;
(c) wherein delay (td) is introduced to an input of at least one of the plural delay detection circuits to differentiate a delay time as detected in the one delay detect ion circuit from a delay time detected by the other delay detection circuits, to differentiate a detected period quantity in the synchronous delay circuit associated with the one delay detection circuit from a detected period quantity detected in the synchronous delay circuit associated with each of the other delay detection circuits, so that, even if the relative relation in the magnitudes of the Propagation delay time (tCTS) of the clock propagation path and the clock period (tCK) of the input clocks is changed to cause discontinuity in clocks from a given one of the sets of the synchronous delay circuits, clocks synchronized with the input clocks are output from the other of the sets of the synchronous delay circuits and routed to the clock propagation path.
According to a fifth aspect, there is provided a semiconductor integrated circuit apparatus for controlling clock signals supplied to a clock propagation path using a synchronous delay circuit, comprising:
(a) a first synchronous delay circuit including a first delay circuit chain for period measurement, that allows propagation of input clock signals and a second delay circuit chain for period reproduction, the second delay circuit chain allowing the clock signals to propagate therethrough by a length corresponding to the length traversed by the clock signals through the first delay circuit chain; and
(b) a first delay detection circuit for detecting the propagation delay time (tCTS) in propagating the clocks from an input node to a preset output node of a clock propagation path and outputting a control signal for controlling the first synchronous delay circuit to cease the propagation of the clock signals for a period of time corresponding to the propagation delay time;
(c) a second synchronous delay circuit including a third delay circuit chain, for period measurement, that allows propagation of input clock signals and a fourth delay circuit chain for period reproduction, the fourth delay circuit chain allowing the clock signals to propagate therethrough by a length corresponding to the length traversed by the clock signals through the third delay circuit chain; and
(d) a second delay detection circuit for detecting the propagation delay time (tCTS) in propagating the clocks from the input node to a preset output node of a clock propagation path and outputting a second control signal for controlling the second synchronous delay circuit to cease the propagation of the clock signals for a period of time corresponding to the propagation delay time;
(e) wherein outputs of the second and fourth delay circuit chains are fed to the input node of the clock propagation path through a switching over unit.
A first delay circuit having a fixed delay time is provided between an output node in the clock propagation path and an input terminal of the second delay detection circuit, and a second delay circuit having the fixed delay time is inserted between an output of the fourth delay circuit chain and an input terminal of the switching over unit.
Delay circuit elements forming the first delay circuit chain comprise clocked inverters on-off controlled by the control signal.
The first and second delay detection circuits are flip-flops being reset and set by an input clock to the clock propagation path and an output clock from the clock propagation path.
A first delay circuit having a fixed delay time is provided between an output node in the clock propagation path and an input terminal of the second delay detection circuit, and
a second delay circuit having the fixed delay time is inserted between an output of the fourth delay circuit chain and an input terminal of the switching over unit.